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Simulation on Plasma
Doping for Shallow Junction Formation |
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Prof. Min Yu, Peking
University,
China |
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Plasma Doping on
68nm CMOS Device Source/Drain Formations |
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Dr. Shu Qin, Micron Technology, Inc., USA |
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Implant and
Annealing Process Integration Issues To Reduce Device Variability
For <10nm p+ & n+ Ultra-Shallow Junctions |
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Mr.
John O. Borland, J.O.B. Technologies, USA |
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Process models for
advanced annealing schemes and their use in device simulation |
Dr.Peter Pichler
Fraunhofer Institute for Integrated Systems and Device Technology
and University of Erlangen-Nuremberg, Germany |
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Novel Diffusion-less Ultra-Shallow Junction Engineering based on
Millisecond Annealing for Sub-30 nm Gate Length Planar Bulk CMOSFET |
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Dr. Kazuya Uejima, NEC Corporation, Japan |
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Recent advances in metallic source/drain MOSFETs |
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Dr.
Emmanuel Dubois,
CNRS, France |
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Nickel Silicidation on Sulfur Implanted Si(100) |
Dr. Qing-Tai Zhao
Institute of Bio- and Nanosystems
and Center
of Nanoelectronic Systems
for Information Technology , Germany |
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Defect
Evolution and C+/F+ Co-implantation in Millisecond Flash annealed
Ultra-Shallow Junctions |
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Dr.
Fuccio Cristiano, LAAS-CNRS, France |
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Extremely Ultrashallow Junctions for a High-Linearity
Silicon-on-Glass RF Varactor-Diode Technology |
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Prof. Lis K. Nanver, Delft University of Technology,
The Netherlands |
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Embedded Silicon Germanium(eSiGe) technologies for 45nm nodes and
beyond |
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Dr. Naoyoshi Tamura, Fujitsu Laboratories LTD., Japan |
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Computer modeling of cluster ion implantation process |
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Dr. Takaaki Aoki, Kyoto University, Japan |
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Ultra-Shallow Junction Formation using Flash Annealing and Advanced
Doping Techniques |
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Mr. Jeff Gelpey,
Mattson
Technology Canada Inc., Canada |
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Advanced Junction Engineering Featuring Millisecond Annealing with
Co-implantation for 45 nm Node High Performance and Low Stand by
Power CMOS Technologies |
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Dr. Tomonari Yamamoto, Fujitsu
Laboratory
Ltd., Japan |
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Effects of Resist Strip and Clean on USJ Performance |
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Dr. Ivan L Berry, Axcelis Technologies, USA |
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Extendibility of NiPt Silicide to the 22-nm Node CMOS Technology |
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Dr. Kazuya Ohuchi, Toshiba, Japan |
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Plasma Doping (PD) for ultra-Shallow Junction |
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Dr. Bunji Mizuno, UJT Lab, Japan |
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Low-Voltage Green Transistor Using Ultra Shallow Junction and
Hetero-Tunneling |
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Dr. Pratik Patel, University of California
(Berkeley), USA |
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Laser Spike Annealing for Advanced CMOS Devices |
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Dr.
Yun
Wang, Ultratech Inc., USA |
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